This invention relates to multiprocessor machine controls, and in particular, to the synchronization of processors and the downloading of instructions between processors.
For further information relating to this application, reference is made to the following companion U.S. patent applications filed concurrently herewith to the common assignee U.S. Ser. No. 420,965, now U.S. Pat. No. 4,589,090, Remote Process Crash Recovery; U.S. Ser. No. 420,988, Process Scheduler in an Electronic Control; U.S. Ser. No. 420,991, Distributed Processing Environment Fault Isolation; U.S. Ser. No. 420,992, now U.S. Pat. No. 4,698,772, Common Control in Multiple Processors By Chaining Tasks; U.S. Ser. No. 420,993, now U.S. Pat. No. 4,475,156; Virtual Machine Control; U.S. Ser. No. 420,994, Task Control Manager; U.S. Ser. No. 420,995, now U.S. Pat. No. 4,521,847, Control System Job Recovery After a Malfunction; U.S. Ser. No. 420,999, Separate Resetting of Processors in a Multiprocessor Control; U.S. Ser. No. 421,006, now U.S. Pat. No. 4,550,382, Filtered Inputs; U.S. Ser. No. 421,008, Multiprocessor Memory Map; U.S. Ser. No. 421,009, Changing Portions of Control in a ROM Based System; U.S. Ser. No. 421,010, now U.S. Pat. No. 4,532,584, Race Control Suspension; U.S. Ser. No. 421,011, now U.S. Pat. No. 4,514,846 Control Fault Detection for Machine Recovery and Diagnostics Prior to Malfunction; U.S. Ser. No. 421,016, now U.S. Pat. No. 4,580,232, Single Point Microprocessor Reset; and U.S. Ser. No. 421,615, Control Crash Diagnostics.
As the complexity of machines and processes increases, so does the complexity of controls for these machines and processes. Even in complex xerographic machines such as described in U.S. Pat. No. 4,186,299, the master processor usually held the control code for all machine functions. This was also true of machines such as described in U.S. Pat. No. 4,338,023. A limited distributed control architecture was used in a machine as described in U.S. Pat. No. 4,306,803. Even then, however, the additional microprocessors handled generally only the servo drive, analog to digital and digital to analog conversion, and power supply functions.
In the prior art control systems, there was usually dedicated process hardware but no dedicated software, or there was dedicated processor software but no dedicated hardware. It would be desirable, therefore, to provide a control system with full hierarchial distributed control having both dedicated software and hardware. That is, all the control codes for each major function of the system would be implemented within the control element for that function.
In a multiprocessor control system, some of the processors or control boards are often dedicated to input/output control. That is, certain of the processors, for example, will monitor switches and sensors as well as provide digital or analog signals to various clutches, motors or other drive components. Therefore, communication between the input/output processors and other control processors is crucial for the timely activation of these drive components. In a multiprocessor control having the various processors interconnected through common channels, communication between the input/output processors and other processors becomes even more critical for the input/output processors to properly perform the control functions.
For example, in any multiprocessor control, sometimes an input/output processor will be required to provide input control information to another processor such as a main control processor. The main control processor will then act on received control information and in turn deliver control information over the shared communication line back to the input/output processor to perform a required control function. Thus, the communication speed over the communication line can be extremely important. If communications over the line become too complex and frequent, vital control information can be excessively delayed either between the input/output processor and the main processor or the main processor and the input/output processor. The result is that a critical machine event or function is not performed within the appropriate timing requirements.
It would be desirable therefore to provide the means to simplify the communication between an input/output processor and another processor over a communication line.
It is, therefore, an object of the present invention to provide a new and improved multiprocessor control. It is another object of the present invention to provide a full hierarchial distributed control system. It is another object of the present invention to provide a new and improved communication means between an input/output processor and another processor without a high risk of failure in providing vital control information, and, in particular, providing essential timing control between the input/output processor and another processor.
Further advantages of the present invention will become apparent as the following description proceeds, and the features characterizing the invention will be pointed out with particularity in the claims annexed to and forming a part of this specification.